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A wheelchair motor-propelled battery-powered ESP32-driven remote control snow plow.

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1/*
2 HardwareSerial.cpp - Hardware serial library for Wiring
3 Copyright (c) 2006 Nicholas Zambetti. All right reserved.
4
5 This library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 This library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with this library; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18
19 Modified 23 November 2006 by David A. Mellis
20 Modified 28 September 2010 by Mark Sproul
21 Modified 14 August 2012 by Alarus
22 Modified 3 December 2013 by Matthijs Kooijman
23*/
24
25#include <stdlib.h>
26#include <stdio.h>
27#include <string.h>
28#include <inttypes.h>
29#include <util/atomic.h>
30#include "Arduino.h"
31
32#include "HardwareSerial.h"
33#include "HardwareSerial_private.h"
34
35// this next line disables the entire HardwareSerial.cpp,
36// this is so I can support Attiny series and any other chip without a uart
37#if defined(HAVE_HWSERIAL0) || defined(HAVE_HWSERIAL1) || defined(HAVE_HWSERIAL2) || defined(HAVE_HWSERIAL3)
38
39// SerialEvent functions are weak, so when the user doesn't define them,
40// the linker just sets their address to 0 (which is checked below).
41// The Serialx_available is just a wrapper around Serialx.available(),
42// but we can refer to it weakly so we don't pull in the entire
43// HardwareSerial instance if the user doesn't also refer to it.
44#if defined(HAVE_HWSERIAL0)
45 void serialEvent() __attribute__((weak));
46 bool Serial0_available() __attribute__((weak));
47#endif
48
49#if defined(HAVE_HWSERIAL1)
50 void serialEvent1() __attribute__((weak));
51 bool Serial1_available() __attribute__((weak));
52#endif
53
54#if defined(HAVE_HWSERIAL2)
55 void serialEvent2() __attribute__((weak));
56 bool Serial2_available() __attribute__((weak));
57#endif
58
59#if defined(HAVE_HWSERIAL3)
60 void serialEvent3() __attribute__((weak));
61 bool Serial3_available() __attribute__((weak));
62#endif
63
64void serialEventRun(void)
65{
66#if defined(HAVE_HWSERIAL0)
67 if (Serial0_available && serialEvent && Serial0_available()) serialEvent();
68#endif
69#if defined(HAVE_HWSERIAL1)
70 if (Serial1_available && serialEvent1 && Serial1_available()) serialEvent1();
71#endif
72#if defined(HAVE_HWSERIAL2)
73 if (Serial2_available && serialEvent2 && Serial2_available()) serialEvent2();
74#endif
75#if defined(HAVE_HWSERIAL3)
76 if (Serial3_available && serialEvent3 && Serial3_available()) serialEvent3();
77#endif
78}
79
80// macro to guard critical sections when needed for large TX buffer sizes
81#if (SERIAL_TX_BUFFER_SIZE>256)
82#define TX_BUFFER_ATOMIC ATOMIC_BLOCK(ATOMIC_RESTORESTATE)
83#else
84#define TX_BUFFER_ATOMIC
85#endif
86
87// Actual interrupt handlers //////////////////////////////////////////////////////////////
88
89void HardwareSerial::_tx_udr_empty_irq(void)
90{
91 // If interrupts are enabled, there must be more data in the output
92 // buffer. Send the next byte
93 unsigned char c = _tx_buffer[_tx_buffer_tail];
94 _tx_buffer_tail = (_tx_buffer_tail + 1) % SERIAL_TX_BUFFER_SIZE;
95
96 *_udr = c;
97
98 // clear the TXC bit -- "can be cleared by writing a one to its bit
99 // location". This makes sure flush() won't return until the bytes
100 // actually got written. Other r/w bits are preserved, and zeroes
101 // written to the rest.
102
103#ifdef MPCM0
104 *_ucsra = ((*_ucsra) & ((1 << U2X0) | (1 << MPCM0))) | (1 << TXC0);
105#else
106 *_ucsra = ((*_ucsra) & ((1 << U2X0) | (1 << TXC0)));
107#endif
108
109 if (_tx_buffer_head == _tx_buffer_tail) {
110 // Buffer empty, so disable interrupts
111 cbi(*_ucsrb, UDRIE0);
112 }
113}
114
115// Public Methods //////////////////////////////////////////////////////////////
116
117void HardwareSerial::begin(unsigned long baud, byte config)
118{
119 // Try u2x mode first
120 uint16_t baud_setting = (F_CPU / 4 / baud - 1) / 2;
121 *_ucsra = 1 << U2X0;
122
123 // hardcoded exception for 57600 for compatibility with the bootloader
124 // shipped with the Duemilanove and previous boards and the firmware
125 // on the 8U2 on the Uno and Mega 2560. Also, The baud_setting cannot
126 // be > 4095, so switch back to non-u2x mode if the baud rate is too
127 // low.
128 if (((F_CPU == 16000000UL) && (baud == 57600)) || (baud_setting >4095))
129 {
130 *_ucsra = 0;
131 baud_setting = (F_CPU / 8 / baud - 1) / 2;
132 }
133
134 // assign the baud_setting, a.k.a. ubrr (USART Baud Rate Register)
135 *_ubrrh = baud_setting >> 8;
136 *_ubrrl = baud_setting;
137
138 _written = false;
139
140 //set the data bits, parity, and stop bits
141#if defined(__AVR_ATmega8__)
142 config |= 0x80; // select UCSRC register (shared with UBRRH)
143#endif
144 *_ucsrc = config;
145
146 sbi(*_ucsrb, RXEN0);
147 sbi(*_ucsrb, TXEN0);
148 sbi(*_ucsrb, RXCIE0);
149 cbi(*_ucsrb, UDRIE0);
150}
151
152void HardwareSerial::end()
153{
154 // wait for transmission of outgoing data
155 flush();
156
157 cbi(*_ucsrb, RXEN0);
158 cbi(*_ucsrb, TXEN0);
159 cbi(*_ucsrb, RXCIE0);
160 cbi(*_ucsrb, UDRIE0);
161
162 // clear any received data
163 _rx_buffer_head = _rx_buffer_tail;
164}
165
166int HardwareSerial::available(void)
167{
168 return ((unsigned int)(SERIAL_RX_BUFFER_SIZE + _rx_buffer_head - _rx_buffer_tail)) % SERIAL_RX_BUFFER_SIZE;
169}
170
171int HardwareSerial::peek(void)
172{
173 if (_rx_buffer_head == _rx_buffer_tail) {
174 return -1;
175 } else {
176 return _rx_buffer[_rx_buffer_tail];
177 }
178}
179
180int HardwareSerial::read(void)
181{
182 // if the head isn't ahead of the tail, we don't have any characters
183 if (_rx_buffer_head == _rx_buffer_tail) {
184 return -1;
185 } else {
186 unsigned char c = _rx_buffer[_rx_buffer_tail];
187 _rx_buffer_tail = (rx_buffer_index_t)(_rx_buffer_tail + 1) % SERIAL_RX_BUFFER_SIZE;
188 return c;
189 }
190}
191
192int HardwareSerial::availableForWrite(void)
193{
194 tx_buffer_index_t head;
195 tx_buffer_index_t tail;
196
197 TX_BUFFER_ATOMIC {
198 head = _tx_buffer_head;
199 tail = _tx_buffer_tail;
200 }
201 if (head >= tail) return SERIAL_TX_BUFFER_SIZE - 1 - head + tail;
202 return tail - head - 1;
203}
204
205void HardwareSerial::flush()
206{
207 // If we have never written a byte, no need to flush. This special
208 // case is needed since there is no way to force the TXC (transmit
209 // complete) bit to 1 during initialization
210 if (!_written)
211 return;
212
213 while (bit_is_set(*_ucsrb, UDRIE0) || bit_is_clear(*_ucsra, TXC0)) {
214 if (bit_is_clear(SREG, SREG_I) && bit_is_set(*_ucsrb, UDRIE0))
215 // Interrupts are globally disabled, but the DR empty
216 // interrupt should be enabled, so poll the DR empty flag to
217 // prevent deadlock
218 if (bit_is_set(*_ucsra, UDRE0))
219 _tx_udr_empty_irq();
220 }
221 // If we get here, nothing is queued anymore (DRIE is disabled) and
222 // the hardware finished tranmission (TXC is set).
223}
224
225size_t HardwareSerial::write(uint8_t c)
226{
227 _written = true;
228 // If the buffer and the data register is empty, just write the byte
229 // to the data register and be done. This shortcut helps
230 // significantly improve the effective datarate at high (>
231 // 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
232 if (_tx_buffer_head == _tx_buffer_tail && bit_is_set(*_ucsra, UDRE0)) {
233 // If TXC is cleared before writing UDR and the previous byte
234 // completes before writing to UDR, TXC will be set but a byte
235 // is still being transmitted causing flush() to return too soon.
236 // So writing UDR must happen first.
237 // Writing UDR and clearing TC must be done atomically, otherwise
238 // interrupts might delay the TXC clear so the byte written to UDR
239 // is transmitted (setting TXC) before clearing TXC. Then TXC will
240 // be cleared when no bytes are left, causing flush() to hang
241 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
242 *_udr = c;
243#ifdef MPCM0
244 *_ucsra = ((*_ucsra) & ((1 << U2X0) | (1 << MPCM0))) | (1 << TXC0);
245#else
246 *_ucsra = ((*_ucsra) & ((1 << U2X0) | (1 << TXC0)));
247#endif
248 }
249 return 1;
250 }
251 tx_buffer_index_t i = (_tx_buffer_head + 1) % SERIAL_TX_BUFFER_SIZE;
252
253 // If the output buffer is full, there's nothing for it other than to
254 // wait for the interrupt handler to empty it a bit
255 while (i == _tx_buffer_tail) {
256 if (bit_is_clear(SREG, SREG_I)) {
257 // Interrupts are disabled, so we'll have to poll the data
258 // register empty flag ourselves. If it is set, pretend an
259 // interrupt has happened and call the handler to free up
260 // space for us.
261 if(bit_is_set(*_ucsra, UDRE0))
262 _tx_udr_empty_irq();
263 } else {
264 // nop, the interrupt handler will free up space for us
265 }
266 }
267
268 _tx_buffer[_tx_buffer_head] = c;
269
270 // make atomic to prevent execution of ISR between setting the
271 // head pointer and setting the interrupt flag resulting in buffer
272 // retransmission
273 ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
274 _tx_buffer_head = i;
275 sbi(*_ucsrb, UDRIE0);
276 }
277
278 return 1;
279}
280
281#endif // whole file
282